There has been a CPRI (Common Public Radio Interface)® as the standard of an interface between a radio equipment control (REC) for carrying out a baseband processing and a radio equipment (RE) for carrying out a radio signal processing in the case that the internal structure of a base station apparatus such as a WCDMA mobile telecommunication system is divided into the radio equipment control and the radio equipment and they are connected to each other through a digital transmission path (see “CPRI Specification”, First Edition, issued on Sep. 30, 2003).
FIG. 7 is a diagram showing a relationship between the radio equipment control and the radio equipment. A base station apparatus 200 includes a radio equipment control 201 and a radio equipment 202, and the radio equipment control 201 and the radio equipment 202 are connected to each other through a digital transmission path 203 for transmitting an electric signal or a light signal.
The radio equipment control 201 is connected to a radio network control (RNC) 210 to carry out the baseband processing. Moreover, the radio equipment 202 serves to carry out a processing in a radio frequency band and to perform a radio communication with a terminal device 220.
In the standard of the CPRI®, a line rate in the digital transmission path 203 is defined, and the reference frequency of the radio equipment 202 is to be synchronized with the reference frequency of the line rate. In the standard of the CPRI, there are 32 basic demand items. Above all, there are the following three demand items for a synchronizing performance.
A first demand is that an fc (line selection cutoff frequency) synchronizing range of 300 Hz in the radio equipment is to be ensured (a demand number of R-17), a second demand is that a jitter stability in the radio equipment (an REC-RE synchronizing system after a synchronization) is to be ensured at ±0.002 ppm (R-18), and a third demand is that a synchronization is to be established in a line clock OFF-ON transient state within 10 seconds (R-30).
However, these three demands are contrary to each other in the case that a synchronizing loop is to be designed by using an ordinary PLL circuit. For example, when the PLL circuit is designed in order to ensure a cutoff frequency demanded in the R-17, it is impossible to ensure a precision in a synchronization which is demanded in the R-18. In order to ensure the precision in the synchronization which is demanded in the R-18, furthermore, it is very hard to establish the synchronization in a time demanded in the R-30. Accordingly, there is a situation in which it is very hard to satisfy these demands at the same time.